The present invention relates to semiconductor memory devices, and particularly to a technology effectively applied to a cache memory housed in a data processing device such as a microprocessor and a microcomputer.
Recently, in accordance with an enhancement of a performance of a low-power consumption microprocessor, an enhancement (high-speed and low-power consumption) of a performance of an on-chip cache memory becomes important. In general, methods of comprising a physical address cache may be classified into three methods, i.e. direct map system, full associative system and set associative system. In the recent microprocessor, considering complexity of hardware, hit rate and access time or the like, the set associative system is employed frequently.
With respect to the set associative system, an example of a 2-way set associative system will be described with reference to FIG. 12.
An offset address in the page within a logical address is used to access a cache data array to read two data from the respective ways to the front of the bus. At the same time, a cache tag array is accessed to read out two tags corresponding to the data thus read out and a virtual page number within the logical address is compared with a physical address transformed by a TLB (translation look aside buffer). If the physical address and the tag value agree with each other (hit), then, data of that way is outputted to the bus.
Since a time in which the TLB is accessed and a hit is detected is generally longer than a time required to read out data from the data array, data read out from the data array cannot be outputted to the bus until the hit signal is made definite, thereby resulting in the access time being increased. Further, since two data have to be read out, it is unavoidable that a power consumption increases.